1. Field of the Invention
The present invention generally relates to a pulse-width-extension circuit and an electronic device including the circuit, and more particularly, to a pulse-width-extension circuit which extends a pulse width of an input pulse signal and to an electronic device such as a memory circuit including the pulse-width-extension circuit.
2. Description of the Related Art
A pulse-width-extension circuit is used in electronic circuits such as memories. More specifically, some static random access memories (SRAMs) have the pulse-width-extension circuit connected with an address-transition detection circuit (ATD circuit). In the SRAM, the ATD circuit detects a transition of an address signal supplied to the memory and produces an address-transition detection signal (ATD signal). The pulse-width-extension circuit extends a pulse width of the ATD signal. The ATD signal whose pulse width has been extended is supplied to, for example, a sense amplifier as a sense-amplifier activating signal. The ATD signal whose pulse width has been extended is also supplied to bit lines in a memory-cell array to rapidly change bit-line signals.
FIG. 1 shows a schematic diagram of a conventional pulse-width-extension circuit for the memory circuit. This pulse-width-extension circuit comprises a delay circuit 2 and a NOR circuit 18. The ATD signal from the ATD circuit is applied to an ATD-signal input port 1. In the delay circuit 2, the ATD signal is delayed such that a delay time of a trailing edge of the ATD signal is longer than that of a leading edge thereof.
The delay circuit 2 comprises serially connected inverters 3 to 8, in which input threshold voltages of the inverters 3, 5, 7 are respectively set to relatively low voltages, and input threshold voltages of inverters 4, 6, 8 are respectively set to relatively high voltages.
Power-source voltage VCC is supplied to power source lines 9, 10, 11. Power-source voltage input ports of the inverters 3, 5, 7 are respectively connected to the power-source lines 9, 10, 11 through resistances 12, 13, 14. Power-source voltage input ports of the inverters 4, 6, 8 are directly connected to a power-source line (not shown). Capacitors 15, 16, 17 are connected between each output of the inverters 3, 5, 7 and a ground.
A rise time of an output signal of the inverter 3 is set to a relatively long time by an RC delay circuit consisting of the resistance 12 and the capacitor 15. A rise time of an output signal of the inverter 5 is set to a relatively long time by an RC delay circuit consisting of the resistance 13 and the capacitor 16. A rise time of an output signal of the inverter 7 is set to a relatively long time by an RC delay circuit consisting of the resistance 14 and the capacitor 17.
An output of the delay circuit 2 and the ATD signal applied to the ATD-signal input port 1 are supplied to the NOR circuit 18 to produce the sense-amplifier activating signal SE.
FIG. 2 shows a timing diagram indicating an operation of the conventional pulse-width-extension circuit shown in FIG. 1 in a case that the ATD signal having a normal pulse width is produced from the ATD circuit based on the transition of the address signal. Part "A" of FIG. 2 is indicated in "FIG. 2-(A)", such representation is used in the following FIGS. 3, 6, and 7. FIG. 2-(A) indicates the ATD signal, FIG. 2-(B) indicates an output S3 of the inverter 3, FIG. 2-(C) indicates an output S4 of the inverter 4, FIG. 2-(D) indicates an output S5 of the inverter 5, FIG. 2-(E) indicates an output S6 of the inverter 6, FIG. 2-(F) indicates an output S7 of the inverter 7, FIG. 2-(G) indicates an output S8 of the inverter 8, and FIG. 2-(H) indicates the sense-amplifier activating signal SE.
In the pulse-width-extension circuit shown in FIG. 1, when no ATD signal (pulse) is produced from the ATD circuit, a level of the ATD-signal input port 1 is kept at a low level (L level). In this situation, the output S3 of the inverter 3 is at a high level (H level), the output level S4 of the inverter 4 is at the L level, the output level S5 of the inverter 5 is at the H level, the output level S6 of the inverter 6 is at the L level, the output level S7 of the inverter 7 is at the H level, the output level S8 of the inverter 8 is at the L level, and the sense-amplifier activating signal SE is at the H level (deactivation level).
Then, when the ATD signal is produced from the ATD circuit (a pulse of the ATD signal rises up), the level of the ATD-signal input port 1 becomes the H level. In this situation, the output S3 of the inverter 3 becomes the L level, the output level S4 of the inverter 4 becomes the H level, the output level S5 of the inverter 5 becomes the L level, the output level S6 of the inverter 6 becomes the H level, the output level S7 of the inverter 7 becomes the L level, the output level S8 of the inverter 8 becomes the H level, and the sense-amplifier activating signal SE becomes the L level (activation level).
As mentioned before, the input threshold voltages of the inverters 3, 5, 7 are respectively set to the relatively low voltages, and the input threshold voltages of the inverters 4, 6, 8 are respectively set to the relatively high voltages, a transition from the L level to the H level in a leading edge of the output S8 of the inverter 8 is carried out in a relatively short time after the ATD signal rises.
Then, when the level of the ATD signal falls, the level of the ATD-signal input port 1 becomes the L level. In this situation, the output S3 of the inverter 3 becomes the H level, the output level S4 of the inverter 4 becomes the L level, the output level S5 of the inverter 5 becomes the H level, the output level S6 of the inverter 6 becomes the L level, the output level S7 of the inverter 7 becomes the H level, the output level S8 of the inverter 8 becomes the L level, and the sense-amplifier activating signal SE returns to the H level (deactivation level).
Since the rise times of the output signals of the inverters 3, 5, 7 are respectively set to relatively long times, and the input threshold voltages of the inverters 4, 6, 8 are respectively set to relatively high voltages, a transition from the H level to the L level in a trailing edge of the output S8 of the inverter 8 is carried out a relatively long time after the level of the ATD signal falls.
In this way, in the pulse-width-extension circuit shown in FIG. 1, the pulse width of the ATD signal from the ATD circuit is extended, and the ATD signal having such an extended pulse width is produced as the sense-amplifier activating signal SE.
However, the conventional pulse-width-extension circuit has suffers from the following drawback:
FIG. 3 shows a timing diagram indicating an operation of the conventional pulse-width-extension circuit shown in FIG. 1 in a case that an abnormal ATD signal which has a short pulse width due to noise, etc., is produced from the ATD circuit. FIG. 3-(A) indicates the ATD signal having the abnormal short pulse width, FIG. 3-(B) indicates the output S3 of the inverter 3, FIG. 3-(C) indicates the output S4 of the inverter 4, FIG. 3-(D) indicates the output S5 of the inverter 5, FIG. 3-(E) indicates the output S6 of the inverter 6, FIG. 3-(F) indicates the output S7 of the inverter 7, FIG. 3-(G) indicates the output S8 of the inverter 8, FIG. 3-(H) indicates the sense-amplifier activating signal SE.
As shown in FIG. 3, in the conventional pulse-width-extension circuit shown in FIG. 1, if the abnormal ATD signal which has a short pulse width due to the noise, etc., is produced from the ATD circuit, the pulse width of the ATD signal is not extended to a required width. Therefore, the sense-amplifier activating signal SE may not have pulse width of sufficient duration to exactly activate the sense amplifier. There is thus a problem that this signal causes a fault operation in the sense amplifier.